Memory integrated circuits (ICs) have a memory array of millions of memory cells used to store electrical charges indicative of binary data. For instance, the presence of an electrical charge in the memory cell typically equates to a binary "1" value and the absence of an electrical charge typically equates to a binary "0" value. The memory cells are accessed via address signals on row and column lines. Once accessed, data is written to or read from the addressed memory cell via digit or bit lines.
The memory cells, row lines, and column lines within the memory array are arranged in a particular layout or configuration that is commonly referred to as the circuit "topology." Circuit topologies vary considerably among variously designed memory ICs.
One common design found in many memory circuit topologies is the "folded bit line" structure. In a folded bit line construction, the bit lines are arranged in pairs with each pair being assigned to complementary binary signals. For example, one bit line in the pair is dedicated to a binary signal DATA and the other bit line is dedicated to handle the complementary binary signal DATA*. (The asterisk notation "*" is used throughout the disclosure to indicate the binary complement.)
The memory cells are connected to either of the bit lines in the folded pair. During read and write operations, the bit lines are driven to opposing voltage levels depending upon the data content being written to or read from the memory cell. For purposes of explanation, the following example describes a read operation of a memory cell holding a charge indicative of a binary "1". The voltage potential of both bit lines in the pair are first equalized to a middle voltage level, such as 2.5 volts. Then, the addressed memory cell is accessed and the charge held therein is transferred to one of the bit lines, raising the voltage of that bit line slightly above the pair counterpart. A sense amplifier, or similar circuit, senses the voltage differential on the bit line pair and further increases this differential by increasing the voltage on the first bit line to, say, 5 volts and decreasing the voltage on the second bit line to, say, 0 volts. The folded bit lines thereby output the data in complementary form.
One version of a folded bit line structure is the twisted bit line structure. FIG. 1 illustrates a twisted bit line structure having bit line pairs D0/D0*-D3/D3* that flip or twist at junctions 20 across the array. Memory cells are coupled to the bit line pairs throughout the array. Representative memory cells 22a-22n and 24a-24n are shown coupled to bit line pair DO/DO*. The twisted bit line structure evolved as a technique to reduce bit-line interference noise during chip operation. Such noise is increasingly more problematic as memory sizes increase. The twisted bit line structure is therefore used in larger memories, such as a 64 Meg DRAM (Dynamic Random Access Memory).
The twisted bit line structure presents a more complex topology than the simple folded bit line construction. Addressing memory cells in the FIG. 1 layout is more involved. For instance, different addresses are used for the memory cells on either side of a twist junction 20. As memory ICs increase in memory capacity, yet maintain or decrease in size, other noise problems and layout constraints force the designer to conceive of more intricate configurations. As a result, the topologies of these circuits become more and more complex, and are more difficult to describe mathematically as each layer of complexity adds additional terms to a topology-describing equation. This in turn may give rise to more complex addressing schemes.
One problem that arises for memory ICs involves testing procedures. It is increasingly more difficult to test memory ICs that have intricate topologies. To test ICs, the memory manufacturer employs a testing machine that is preprogrammed by the manufacturer with a complex boolean function that describes the topology of the memory IC. This boolean function is derived by the manufacturer. Conventional testing machines are capable of handling up to 6-bit addresses. As topologies grow more complex, however, the 6-bit addresses are incapable of fully addressing all individual cells for some test patterns. This renders the testing apparatus ineffective. Furthermore, if a user wishes to trouble shoot a particular memory device after some period of use, it is very difficult to derive the necessary boolean function for input to the testing machine without consulting the manufacturer.
The testing problem becomes more manifest when a form of compression is used during testing to accelerate the testing period. It is common to write test patterns of all "1"s or all "0"s to a group of memory cells simultaneously. Consider the following example test pattern of writing all "1"s to the memory cells in the twisted bit line pairs of FIG. 1. Under the testing compression, one bit is used to address all four bit line pairs D0/D0*, D1/D1*, D2/D2*, and D3/D3*. Under this conventional addressing scheme, the task of placing "1"s in all memory cells is impossible because it cannot be discerned from a single address bit whether the memory cell, in order to receive a "1", needs to have a binary "1" or "0" placed on the bit line connected to the memory cell. Accordingly, the testing machines may not adequately test memory ICs of complex topologies. Conversely, it is less desirable to test memory ICs on a per cell basis as the testing period is too long.
It is therefore an object of this invention to provide a memory IC that facilitates such testing, as well as methods for testing semiconductor memory ICs having complex circuit topologies.